Computer Vision Architectures and Algorithms


In the 1980s we worked on a project with Hughes Research Laboratories (Now HRL) on a hierarchical parallel computer architecture for computer vision. The architecture had three levels to perform the “iconic to symbolic transformation” from input images to labeled images. We developed parallel algorithms for edge detection, region growing, histogram based segmentation, etc. that operated on a pixel-per-processor low level engine. This was then followed by a mid-level signal processing array, and a top level symbolic processor. Together the architecture was called the “Image Understanding Architecture” .

  1. C.C. Weems, S.P. Levitan, A.R. Hanson, E.M. Riseman, J.G. Nash, D.B. Shu, "The Image Understanding Architecture," International Journal of Computer Vision, Vol. 2, pp. 251-282 (1989).
  2. D. Rana, C.C. Weems, S.P. Levitan, "An Easily Reconfigurable, Circuit Switched Connection Network," IEEE International Symposium on Circuits and Systems (ISCS'98), Helsinki University of Technology, Vol. 1, pp. 247-250, Espoo, Finland, June 7-9, 1988.
  3. C.C. Weems, S.P. Levitan, A.R. Hanson, E.M. Riseman, "The Image Understanding Architecture," Proceedings of the DARPA Image Understanding Workshop, Vol. 2, pp. 483-496, Los Angeles, CA, Feb. 1987.
  4. Processing Using a Content Addressable Array Parallel Processor," Proceedings of the IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR'85), pp. 598-607, San Francisco, CA, June 19-29, 1985.
  5. C.I. Wu, J.G. Nash, S.P. Levitan, C.C. Weems, "Parallel Processing of Iconic to Symbolic Transformation of Images," D.I. Moldovan, Proceedings of the IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR'85), pp. 257-264, San Francisco, CA, June 19-29, 1985.
  6. D.T. Lawton, S.P. Levitan, C.C. Weems, E.M. Riseman, A.R. Hanson, "Iconic to Symbolic Processing Using the Content Addressable Array Parallel Processor," Proceedings of the 1984 DARPA Fall Image Understanding Workshop, New Orleans, LA, Oct. 1984.
  7. D.T. Lawton, S.P. Levitan, C.C. Weems, E.M. Riseman, A.R. Hanson, M. Callahan, "Iconic to Symbolic Processing Using a Content Addressable Array Parallel Processor," Applications of Digital Image Processing VII, Proceedings of the SPIE, Vol. 504, pp. 92-111, San Diego, CA, Aug. 12-24, 1984.
  8. C.C. Weems, S.P. Levitan, C.C. Foster, E.M. Riseman, D.T. Lawton, A.R. Hanson, "Development and Construction of a Content Addressable Array Parallel Processor for Knowledge-Based Image Interpretation," AFOSR Workshop on Algorithm-Guided Parallel Architectures for Automatic Target Recognition, Leesburg, VA, July 16-18, 1984.
  9. C.C. Weems, S.P. Levitan, C.C. Foster, "Titanic: A VLSI Based Content Addressable Parallel Array Processor," IEEE International Conference on Computer Circuits (ICCC'82), pp. 236-239, New York, NY, Sept. 29 - Oct. 1, 1982.