VLSI Computer Aided Design



We have performed several investigations on design capture, simulation, synthesis verification and testing of digital systems. Our early work focused on VHDL as a design and simulation language expanding to architectural synthesis, binding and allocaton. We studied timing verification of asynchronous systems as well as model abstraction for formal verification. We developed techniques for device testing based on the signatures and analysis of transient power supply signals



  1. Steven P. Levitan, “You Can Get There From Here: Connectivity of Random Graphs on Grids,” Proceedings of the 44th IEEE/ACM Design Automation Conference (DAC’07), (WACI Session) pp. 272-273, San Diego, CA, June 4-8, 2007.
  2. J.A. Martinez, S.P. Levitan, D.M. Chiarulli, “Nonlinear Model Order Reduction Using Remainder Functions,” IEEE Computer Society, Design, Automation and Test in Europe (DATE ’06) ICM, IP2 Interactive presentations, Paper No. 791, MESSE Munich, Germany, March 6-10, 2006.
  3. N. Wattanapongsakorn, S.P. Levitan, "Reliability Optimization Models for Fault-Tolerant Distributed Systems," The IEEE Annual Reliability and Maintainability Symposium (RAMS 2001), pp. 193-199, Philadelphia, PA, January 22-25, 2001.
  4. "CAD Tools and Modeling Challenges for Optoelectronic Systems," TIMA Laboratory, Grenoble, France, December 15, 2000. (Presentation)
  5. Y.-W. Hsieh, S.P. Levitan, "Abstraction Techniques for Verification of Multiple Tightly Coupled Counters, Registers and Comparators," IEEE Symposium on High Level Design Validation and Test (HLDVT 2000), pp. 133-138, Berkeley CA, November 8-11, 2000.
  6. "Multi-Level Simulation of Mixed-Technology Micro-Systems", Marconi International, U.K. September 14, 2000. (Presentation)
  7. N. Wattanapongsakorn, S.P. Levitan, "Integrating Dependability Analysis into the Real-Time System Design Process," The IEEE Annual Reliability and Maintainability Symposium (RAMS 2000), pp. 327-334, Los Angeles, CA, January 24-27, 2000.
  8. Y.-W. Hsieh, S.P. Levitan,"NFSM Generation for Semantics Based Model Abstraction," Fourth Annual IEEE International Workshop on High Level Design Validation and Test (HLDVT'99), pp. 138-145, San Diego, CA, November 4-6, 1999.
  9. J.F. Plusquellic, D.M. Chiarulli, S.P. Levitan, "Time- and Frequency-Domain Transient Signal Analysis for Defect Detection in CMOS Digital IC's," IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications, Vol. 46, No. 11, pp. 1390-1394, November 1999.
  10. K. Choi, S.P. Levitan, "A Flexible Datapath Allocation Method for Architectural Synthesis," Transactions on Design Automation of Electronic Systems, Vol. 4, No. 4, pp. 376-404, October 1999.
  11. J.F. Plusquellic, D.M. Chiarulli, S.P. Levitan, "An Automated Technique to Identify Defective CMOS Devices Based on Linear Regression Analysis of Transient Signal Data," (IDDQ'98), pp. 32-36, San José, CA, Nov. 12-13, 1998.
  12. J. F. Plusquellic, D. M. Chiarulli, S. P. Levitan, "Characterization of CMOS Defects Using Transient Signal Analysis," IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'98), pp. 93-101, Austin, TX, Nov. 2-4, 1998.
  13. Y.-W. Hsieh, S.P. Levitan, "Model Abstraction for Formal Verification," IEEE Design Automation and Test Europe (DATE'98), pp. 140-147, Paris, France, Feb. 23-26, 1998.
  14. Y.-W. Hsieh, S.P. Levitan,"Control/Data-Flow Analysis for VHDL Semantic Extraction," Journal of Information Science and Engineering, Vol. 14, No. 3, pp. 547-565, 1998.
  15. J. F. Plusquellic, D. M. Chiarulli, S. P. Levitan, "Identification of Defective CMOS Devices Using Correlation and Regression Analysis of Frequency Domain Transient Signal Data," IEEE International Test Conference (ITC'97), pp. 40-49, Washington, DC, Nov. 1-6, 1997.
  16. Y.-W. Hsieh, S.P. Levitan, "Control/Data-Flow Analysis for VHDL Semantic Extraction," Asia Pacific Conference on Hardware Description Languages (APCHDL'97), pp. 68-75, Tsing Hua University, Hsin-Chu, Taiwan, Aug. 18-20, 1997.
  17. J. F. Plusquellic, D. M. Chiarulli, S. P. Levitan, "Digital Integrated Circuit Testing Using Transient Signal Analysis," IEEE International Test Conference (ITC'96), pp. 481-490, Washington, DC Oct. 20-25, 1996.
  18. S.T. Frezza, S.P. Levitan, P.K. Chrysanthis, "Linking Requirements and Design Data for Automated Functional Evaluation," Computers in Industry Special Issue on Electronic Design Process, Vol. 30, No. 1, pp. 13-25, (Elsevier) Sept. 1996.
  19. D.W. Bouldin, P. Banerjee, M.A. Bayoumi, G. Borriello, F. Catthoor, B. Courtois, S.R. Das, H.L. Davidson, G. DeMicheli, D. Hill, M. Ismail, W.H. Joyner, N. Kanopoulos, S.P. Levitan, J.F. McDonald, A. Mukherjee, Y. Nakamura, V.G. Oklobzija, L.M. Patnaik, N. Ranganathan, B.J. Sheu, C.E. Stroud, D.E. Thomas, C.K. Wong, C.Y. Wu, T. Yanagawa, "Foreword for March 1996 issue," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 4, No. 1, 1-12 Mar. 1996.
  20. K.M. Choi, S.P. Levitan, "A Robust Datapath Allocation Method for Realistic System Design," 4th IEEE International Conference on VLSI and CAD (ICVC'95), Seoul, Korea, Oct. 15-18, 1995.
  21. J.F. Plusquellic, D.M. Chiarulli, S.P. Levitan, "Digital IC Device Testing by Transient Signal Analysis (TSA)," IEE Electronics Letters, Vol. 31, No. 18, pp. 1568-1570, 31 Aug. 1995.
  22. S.T. Frezza, S.P. Levitan, P.K. Chrysanthis, "Requirements-Based Design Evaluation," Proceedings of the 32nd IEEE/ACM Design Automation Conference (DAC'95), pp. 76-81, San Francisco, CA, June 11-15, 1995.
  23. "The Impact of the World Wide Web on Electronic Design and EDA," (panelist), 32nd IEEE/ACM Design Automation Conference, p. 586, San Francisco, CA, June 1995. (Presentation)
  24. "VHDL Research at the University of Pittsburgh," Digital Equipment Corporation, Littleton, MA, May 1995. (Presentation
  25. K.M. Choi, S.P. Levitan, "Exploration of Area and Performance Optimized Datapath Design Using Realistic Cost Metrics," IEEE International Symposium on Circuits and Systems (ISCAS'95), Vol. 2, pp. II: 1049-1052, Seattle, WA, Apr. 29-May 3, 1995.
  26. S.T. Frezza, S.P. Levitan, P.K. Chrysanthis, "Requirements Based Functional Evaluation," 1995 NSF Design and Manufacturing Grantees Conference, (poster), pp. 539-540, University of California, San Diego, La Jolla, CA, Jan. 4-6 1995.
  27. "CAD for Programmable Logic Devices," Budker Institute of Nuclear Physics, Novosibirsk, Russia, Oct. 1994. (Presentation)
  28. "VHDL Synthesis - Current Reality & Future Vision," VHDL International Users Forum, San José, CA, Oct. 1993 (Panel Chair).
  29. S.T. Frezza, S.P. Levitan, "SPAR: A Schematic Place and Route System," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 12, No. 7, pp. 956-973, July 1993.
  30. Y.-W. Hsieh, S.P. Levitan, B.M. Pangrle, "Incorporating Interconnection Delays in VHDL Behavioral Synthesis," Fourth ACM/SIGDA Physical Design Workshop (PDW'93), pp. 175-186, Lake Arrowhead, CA, Apr. 19-21, 1993.
  31. "Temporal Analysis of Time Bounded Digital Systems," IFIP WG10.2 Advanced Research Working Conference on Correct Hardware Design and Verification Methods, (CHARME'93), 1993.
  32. A.R. Martello, S.P. Levitan, "Temporal Specification Verification via Causal Reasoning," ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (Tau'92), Princeton, NJ, Mar. 18-20, 1992.
  33. "Keystone: A VHDL Simulation and Synthesis Environment for VLSI Design," IBM Thomas J. Watson Research Center, Hawthorne, NY, Oct. 1991.
  34. S.P. Levitan, B. Pangrle, Y.-W. Hsieh, "Architectural Synthesis via VHDL," Third ACM/SIGDA Physical Design Workshop (PDW'91), Nemacolin Woodlands, PA, May 20-23, 1991.
  35. A.R. Martello, S.P. Levitan, "Causal Timing Verification," ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU'90), Vancouver, BC, Aug. 15-17, 1990.
  36. A.R. Martello, S.P. Levitan, D.M. Chiarulli, "Timing Verification Using HDTV," Proceedings of the 27th ACM/IEEE Design Automation Conference (DAC'90), pp. 118-123, Orlando, FL, June 1990.
  37. "The Keystone Silicon Synthesis Project," Viewlogic Systems, Marlboro, MA, Jan. 1990. (Presentation)
  38. "Silicon Synthesis: A VHDL Approach," IEEE Student Chapter, Pennsylvania State University, State College, PA, Nov. 1989. (Presentation)
  39. "Experiences Using VHDL in the Classroom," VHDL Users Group Meeting, Sheraton Hotel, Redondo Beach, CA, Oct. 1989. (Presentation)
  40. "Synthesis of CMOS Structures from VHDL," VHDL Methods Workshop, University of Virginia, Charlottesville, VA, Aug. 1989. (Presentation)
  41. "VLSI Curriculum: CAD for VLSI," VLSI Education Conference & Exposition, pp. 181-182, Santa Clara, CA, July 1989.
  42. S.P. Levitan, R.M. Owens, M.J. Irwin, "A VLSI CAD System for VHDL," Colorado Microelectronics Conference, pp. 1-8, Antlers Hotel, Colorado Springs, CO, Mar. 30-31, 1989.
  43. "From VHDL to Layout," VHDL Users Group Meeting, Sheraton Hotel, Redondo Beach, CA, Oct. 1988. (Presentation)
  44. "An Integrated Capture and Simulation Tool for Digital Designs," The Pennsylvania State University, State College, PA, Sept. 1988. (Presentation)
  45. D. Rana, C.C. Weems, S.P. Levitan, "An Easily Reconfigurable, Circuit Switched Connection Network," IEEE International Symposium on Circuits and Systems (ISCS'98), Helsinki University of Technology, Vol. 1, pp. 247-250, Espoo, Finland, June 7-9, 1988.
  46. "Architectures and VLSI," Workshop on Special Computer Architectures for Robotics, International Conference on Robotics and Automation, Philadelphia, PA, Apr. 1988. (Presentation)
  47. S.P. Levitan, J.T. Cain, "Teaching Computer Architecture as Engineering Design with VLSI," 21st Annual IEEE Hawaiian International Conference on Systems Sciences (HICSS'88), Vol. 1, pp. 85-90, Kona, HI, Jan. 5-8, 1988.
  48. "Teaching VLSI as a Capstone Course," NSF/MOSIS Undergraduate Education Workshop, National Science Foundation, Washington, DC, Nov. 1987. (Presentation)
  49. D. Rana, S.P. Levitan, D.A. Carlson, C.E. Hutchinson, "A Testable, Asynchronous Systolic Array Implementation of an IIR Filter," IEEE Custom Integrated Circuits Conference (CICC'86), pp. 90-93, Rochester, NY, May 12-15 1986.
  50. S.P. Levitan, "Evaluation Criteria for Communication Structures in Parallel Architectures," 1985 International Conference on Parallel Processing (ICPP'85), pp. 147-154, St. Charles, IL Aug. 20-23, 1985.
  51. C.C. Weems, D.T. Lawton, S.P. Levitan, E.M. Riseman, A.R. Hanson, "Iconic and Symbolic Processing Using a Content Addressable Array Parallel Processor," Proceedings of the IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR'85), pp. 598-607, San Francisco, CA, June 19-29, 1985.
  52. C.I. Wu, J.G. Nash, S.P. Levitan, C.C. Weems, "Parallel Processing of Iconic to Symbolic Transformation of Images," D.I. Moldovan, Proceedings of the IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR'85), pp. 257-264, San Francisco, CA, June 19-29, 1985.
  53. D.T. Lawton, S.P. Levitan, C.C. Weems, E.M. Riseman, A.R. Hanson, "Iconic to Symbolic Processing Using the Content Addressable Array Parallel Processor," Proceedings of the 1984 DARPA Fall Image Understanding Workshop, New Orleans, LA, Oct. 1984.
  54. D.T. Lawton, S.P. Levitan, C.C. Weems, E.M. Riseman, A.R. Hanson, M. Callahan, "Iconic to Symbolic Processing Using a Content Addressable Array Parallel Processor," Applications of Digital Image Processing VII, Proceedings of the SPIE, Vol. 504, pp. 92-111, San Diego, CA, Aug. 12-24, 1984.
  55. C.C. Weems, S.P. Levitan, C.C. Foster, E.M. Riseman, D.T. Lawton, A.R. Hanson, "Development and Construction of a Content Addressable Array Parallel Processor for Knowledge-Based Image Interpretation," AFOSR Workshop on Algorithm-Guided Parallel Architectures for Automatic Target Recognition, Leesburg, VA, July 16-18, 1984.
  56. "Parallel Algorithms and Architectures: A Programmers Perspective," Taxonomy of Parallel Algorithms Workshop, Los Alamos National Laboratory, Santa Fe, NM, Nov. 1983. (Presentation)
  57. "Topics in Computer Architecture," Smith College, Northampton, MA, Feb. 1983. (Presentation)
  58. S.P. Levitan, "Algorithms for a Broadcast Protocol Multiprocessor," 3rd IEEE International Conference on Distributed Computing Systems (ICDCS'82), pp. 666-671, Miami/Ft. Lauderdale, FL, Oct. 18-22, 1982.
  59. C.C. Weems, S.P. Levitan, C.C. Foster, "Titanic: A VLSI Based Content Addressable Parallel Array Processor," IEEE International Conference on Computer Circuits (ICCC'82), pp. 236-239, New York, NY, Sept. 29 - Oct. 1, 1982.
  60. S.P. Levitan, C.C. Foster, "Finding an Extremum in a Network," 9th ACM/IEEE Annual International Symposium on Computer Architecture (ISCA'82), pp. 321-325, Austin, TX, Apr. 26-29, 1982.